1. Technical Field
Various embodiments of the present disclosure generally relate to apparatuses and methods of distributing addresses in memory devices and, more particularly, to apparatuses and methods of distributing addresses in memory devices for mitigating write disturbance.
2. Related Art
Recently, memory devices using a semiconductor material have been in increasing demand with the development of portable systems such as mobile phones. The memory devices may be typically categorized as either volatile memory devices or nonvolatile memory devices. In particular, since most portable systems tend to employ a large memory capacity, nonvolatile memory devices which retain stored data even when power supply is interrupted have been widely used in various portable systems. The volatile memory devices may include static random access memory (SRAM) devices and dynamic random access memory (DRAM) devices. The nonvolatile memory devices may include ferroelectric random access memory (FeRAM) devices, magnetic random access memory (MRAM) devices, resistive random access memory (RRAM) devices, and phase change memory (PCM) devices.
The PCM devices among the nonvolatile memory devices have been known as attractive nonvolatile memory devices. This is because the PCM devices have a relatively simple cell structure as compared with other nonvolatile memory devices and exhibit a relatively high operation speed like DRAM devices which belong to the volatile memory devices. Furthermore, the PCM devices are very attractive as next generation nonvolatile memory devices because manufacturing costs of the PCM devices are relatively low as compared with other nonvolatile memory devices. A unit cell of PCM devices may be located at a cross point of a word line and a bit line to include a switching element and a data storage element which are coupled in series. The data storage element may include a lower electrode electrically coupled to the switching element, a phase changeable material pattern disposed on the lower electrode, and an upper electrode disposed on the phase changeable material pattern.
In the PCM devices, if a write current flows through the switching element and the lower electrode to perform a write operation, joule heat may be generated at an interface between the lower electrode and the phase changeable material pattern. The joule heat generated at the interface between the lower electrode and the phase changeable material pattern may change a phase of the phase changeable material pattern into an amorphous state or a crystalline state to perform a write operation. While the PCM device operates in a write mode for performing write operations, logical addresses may be inputted to the PCM device and the logical addresses may be changed into physical addresses. If write operations are performed to sequentially write data into a plurality of memory cells physically coupled to a single word line or a single bit line, two adjacent memory cells may be successively written with data. In such a case, joule heat generated in one of the two adjacent memory cells may directly affect the other one of the two adjacent memory cells to cause a write disturbance.